As an electrically programmable and erasable non-volatile semiconductor device, EEPROM (Electrically Erasable and Programmable Read Only Memory) is widely used. Storage devices typified by a currently widely-used flash memory has an electrically-conductive floating gate electrode or a trap insulating film surrounded by an oxide film below a gate electrode of a MISFET, a charge accumulated state in the floating gate or the trap insulating film serves as stored information, and it is read as a threshold value of the transistor. The trap insulating film serves as an insulating film which can accumulate charge, and examples thereof include a silicon nitride film. The threshold value of the MISFET (Metal Insulator Semiconductor Field Effect Transistor) is shifted by injection/release of charge into/from such a charge accumulating region to operate it as a storage element. When a trap insulating film such as a silicon nitride film is used as the charge accumulating region, as compared with a case in which an electrically-conductive floating gate film is used as the charge accumulating region, there are such advantages as that the reliability of data retention is excellent since charge is discretely accumulated, oxide films above/below the silicon nitride film can be thinned since the reliability of data retention is excellent, and the voltages of programming/erasing operations can be reduced.
Japanese Patent Application Laid-Open Publication No. 2008-244163 (Patent Document 1) describes a technique about a memory cell of a non-volatile memory in which, on a channel region, a tunnel insulating film 102 formed of a silicon oxynitride film, a charge accumulating layer 103 formed of a hafnium oxynitride film, and a block insulating film 104 formed of an alumina film are sequentially disposed, and a control gate electrode 105 is disposed on the block insulating film 104.
Japanese Patent Application Laid-Open Publication No. 2004-336044 (Patent Document 2) describes, in FIG. 2, etc., a technique in which a gate stack is provided on a channel region, and the gate stack is formed by sequentially stacking a tunneling oxide film 42 formed of a silicon oxide film, a first trapping material film 44 formed of, for example, HfO2, a first insulating film 46 formed of an aluminum oxide, and a gate electrode 48. Moreover, FIG. 3 etc. describe a technique in which a first oxide film 50 which is an aluminum oxide film is provided between the tunneling oxide film 42 and the first trapping material film 44, a second insulating film 52 which is an aluminum oxide film is provided between the first trapping material film 44 and the first insulating film 46, and the first insulating film 46 is formed of, for example, HfO2.
Japanese Patent Application Laid-Open Publication No. 2010-10566 (Patent Document 3) describes, in FIG. 6 etc., a technique of forming a gate electrode by sequentially forming, on a silicon substrate 23, a silicon oxide film 25, an aluminum oxide film 27, a LaHfO film 28, an aluminum oxide film 29, and a poly-Si film 30 for a gate electrode and then processing a stacked film thereof using the lithography technique and the RIE technique.